Kode:
TestBench.v:
// ============================================================
//
// Traffic light tester module.
//
// We clock the device as usual, supply reset, and eventually "push
// the walk button" to activate the traffic light.
//
// ============================================================
// `timescale 1 ns / 1 ns
module TestBench;
reg clk; // Clock into the FPGA
reg walk; // A button that causes the walk light to go on
reg reset; // The reset line to your design
wire green; // The green light on Dodge Street
wire yellow; // The yellow light on ...
wire red; // The red light on ...
wire go; // The walk light for the pedestrian
wire stop; // The "don't walk" light
// Here is your FPGA chip
Traffic yourChip( reset, clk, walk, green, yellow, red, go, stop );
// Provide clocking to the FPGA
always
begin
#10 clk = ~clk;
end
// Start up code.
initial
begin
clk = 0;
walk = 0;
reset = 1;
#100 reset = 0;
end
// Eventually we want to "push the walk button" which causes the
// traffic lights to cycle yellow, red, then back to green.
// Also, we want to stop the sim at some point too.
initial
begin
#1000 walk = 1;
#100 walk = 0;
#100000 $stop;
end
endmodule // QuasiTestBench
clockDivder.v:
module clockDivider(
input wire clock,
input wire reset,
output wire dividedClk
);
reg [127:0] counter;
always @(posedge clock or posedge reset)
begin
if(reset == 1)
counter <=0;
else
counter <= counter + 1;
end
assign dividedClk = counter[127];
endmodule
Lalu Lintas.v:
module Traffic( reset, clock, walk, green, yellow, red, walkLight, handLight);
input wire reset;
input wire clock;
input wire walk;
output reg green, yellow, red, walkLight, handLight;
reg[2:0] state;
reg[3:0] count;
//we want some kind of state machine here.
//let's define some states
parameter s0 = 0 //green
, s1=1 //yellow
, s2=2; //red
reg[3:0] timeButtonPushed;
//clockDivider myClock(clock, reset);
always @(posedge clock or posedge reset)
begin
if (reset == 1)
begin
state <= s0; //default to green light on reset.
handLight = 1;
green = 1;
timeButtonPushed = 0;
count <= 0;
end
else
case(state)
s0:
begin
if(walk == 1)
begin
//compute 10s timeout before switch to yellow
//requires us to capture some info about time button pushed
timeButtonPushed = count; //record time button was pushed
end
else
if(timeButtonPushed == (count - 10))
begin
state = s1; //We've reached countdown state set light to yellow.
green = 0;
yellow = 1;
end
count = count + 1;
end
s1:
begin
if(timeButtonPushed == (count - 15)) //We've reached timeout for yellow light.
begin
state = s2; //move to red state
handLight = 0;
walkLight = 1;
red = 1;
end
count = count + 1;
end
s2:
begin
if(timeButtonPushed == count - 45)
begin
state = s0; //move back to green state
red = 0;
walkLight = 0;
handLight = 1;
green = 0;
timeButtonPushed = 0;
end
count = count + 1;
end
default: state <= s0;
endcase
end
endmodule
Saya telah mencoba membuat instance clockDivider di TestBench, dan saya juga mencoba membuat instance di Traffic.v dengan mencoba memasukkannya di antara jam dan kabel input clk di Traffic.v
Idealnya saya ingin solusi yang menunjukkan kepada saya cara yang benar untuk menyambungkan clockDivider dengan benar, namun jika ada cara lain--bahkan jika hack-ish untuk menyelesaikannya, saya akan menghargainya.
Saya juga mencoba melupakan clockDivider.v sepenuhnya dan mengganti kode jam dengan ini:
reg [127:0] counter;
always
begin
if(reset == 1)
counter <=0;
else if(counter == 126)
assign clk = ~clk;
else
counter <= counter + 1;
end
Namun hal itu tampaknya juga gagal.
